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Disambiguation of "Wong, S."

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Reconfigurable high performance architectures: How much are they ready for safety-critical applications?

, , , , , , , , , , and . ETS, page 1-8. IEEE, (2014)

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Walter Wong

Limsoon Wong

Wei-chwen Wong

Yu Man James Wong

Hoi-Ming Wong

 

Other publications of authors with the same name

First Observation of Ultra-high Polarization (~ 108 μC/cm²) in Nanometer Scaled High Performance Ferroelectric HZO Capacitors with Mo Electrodes., , , , , , , , , and 2 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)4 Bits/cell Hybrid 1F1R for High Density Embedded Non-Volatile Memory and its Application for Compute in Memory., , , , , , , and . VLSI Technology and Circuits, page 244-245. IEEE, (2022)Impact of III-V and Ge Devices on Circuit Performance., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (7): 1189-1200 (2013)Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array., , , and . JETC, 9 (1): 9:1-9:14 (2013)TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (4): 521-534 (2016)TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits., , , , , and . CoRR, (2015)8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory., , , , , , , , and . VLSI Technology and Circuits, page 314-315. IEEE, (2022)Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design., , , and . ISQED, page 342-346. IEEE, (2010)The analysis of the performance of the exchange rate of the Australian dollar using waveform dictionaries., and . ISSPA, page 195-198. IEEE, (1999)Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)