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Fault-based automatic test generator for linear analog circuits.

, , , and . ICCAD, page 88-91. IEEE Computer Society / ACM, (1993)

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Manufacturability of Mixed Signal Systems., and . VLSI Design, page 608. IEEE Computer Society, (1999)Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks., , and . DAC, page 403-408. ACM Press, (1997)A Survey of Test Techniques for MCM Substrates., , and . J. Electron. Test., 10 (1-2): 27-38 (1997)Environment-Adaptive Concurrent Companding and Bias Control for Efficient Power-Amplifier Operation., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (3): 607-618 (2011)Accurate Linear Model for SET Critical Charge Estimation., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1161-1166 (2009)Low Power Neural Network Accelerators Using Collaborative Weight Tuning and Shared Shift-Add optimization., , , and . MWSCAS, page 1-4. IEEE, (2022)Predicting die-level process variations from wafer test data for analog devices: A feasibility study., , , , , and . LATW, page 1-6. IEEE Computer Society, (2013)Optimal INL/DNL testing of A/D converters using a linear model., and . ITC, page 358-366. IEEE Computer Society, (2000)Low cost back end signal processing driven bandwidth interleaved signal acquisition using free running undersampling clocks and mixing signals., , and . ITC, page 1-10. IEEE Computer Society, (2014)A self-tuning architecture for buck converters based on alternative test., , , and . ITC, page 1-10. IEEE Computer Society, (2014)