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Disambiguation of "Fujiwara, Hideo"

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Test Synthesis for Datapaths Using Datapath-Controller Functions.

, , , and . Asian Test Symposium, page 294-299. IEEE Computer Society, (2003)

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Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order., , , and . GD, volume 1547 of Lecture Notes in Computer Science, page 183-197. Springer, (1998)An approach to test synthesis from higher level., and . Integr., 26 (1-2): 101-116 (1998)System-on-chip test scheduling with reconfigurable core wrappers., and . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 305-309 (2006)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)A cost optimal parallel algorithm for weighted distance transforms., , , and . Parallel Comput., 25 (4): 405-416 (1999)A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings., , , and . J. Parallel Distributed Comput., 62 (5): 865-884 (2002)Effect of BIST Pretest on IC Defect Level., , and . IEICE Trans. Inf. Syst., 89-D (10): 2626-2636 (2006)Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints., , , and . IEICE Trans. Inf. Syst., 91-D (3): 807-814 (2008)Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths., , , , and . IEICE Trans. Inf. Syst., 88-D (8): 1940-1947 (2005)Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design., , and . IEICE Trans. Inf. Syst., 94-D (7): 1430-1439 (2011)