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Disambiguation of "Hsu, Steven K."

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A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS.

, , , , and . ESSCIRC, page 316-319. IEEE, (2007)

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Eric Hsu

Yüanfang Hsü

Oscar Hsu

Eugene Hsu

Allen Hsu

 

Other publications of authors with the same name

A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 41 (1): 256-264 (2006)An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS., , , , , and . ISSCC, page 1785-1797. IEEE, (2006)16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS., , , , , , , , , and . ISSCC, page 278-279. IEEE, (2014)A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 56 (4): 1082-1092 (2021)25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range., , , , , , , , , and 4 other author(s). ISSCC, page 396-398. IEEE, (2020)A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS., , , , and . ESSCIRC, page 316-319. IEEE, (2007)An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS., , , , , , and . ISSCC, page 1-3. IEEE, (2022)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)