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Disambiguation of "Harigai, Naohiro"

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A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS.

, , , , , and . ASP-DAC, page 553-554. IEEE, (2012)

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Other publications of authors with the same name

A CMOS PWM Transceiver Using Self-Referenced Edge Detection., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (6): 1145-1149 (2015)Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . ASP-DAC, page 103-104. IEEE, (2013)A clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . VLSIC, page 142-143. IEEE, (2012)A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines., , , and . IEICE Trans. Electron., 96-C (6): 920-922 (2013)A low-offset cascaded time amplifier with reconfigurable inter-stage connection., , , and . IEICE Electron. Express, 11 (10): 20140203 (2014)An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation., , , , and . A-SSCC, page 201-204. IEEE, (2011)A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS., , , , , and . ASP-DAC, page 553-554. IEEE, (2012)Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements., , , , , , and . ISOCC, page 146-149. IEEE, (2011)Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption., , and . IEICE Electron. Express, 10 (11): 20130289 (2013)CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation., , , , and . IEEE J. Solid State Circuits, 47 (11): 2701-2710 (2012)