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Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework.

A. Sachid, R. Thakker, C. Sathe, M. Baghini, D. Sharma, V. Rao, and M. Patil. ISQED, page 713-720. IEEE, (2010)

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V Ramgopal Rao

Ramgopal Sachdev

Yadlapalli Venkateswara Rao

Balakrishna Rao

Bharathi Vasudeva Rao

Other publications of authors with the same name

Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thickness.Y. Kobayashi, K. Kakushima, P. Ahmet, V. Rao, K. Tsutsui, and H. Iwai. Microelectron. Reliab., 50 (3): 332-337 (2010)Induced Stress Enhancement Using U-shaped Arms in a 3-Axis Piezoresistive MEMS Accelerometer.M. Said, F. Tounsi, B. Mezghani, A. Ahmed, S. Pandit, R. Patkar, P. Dixit, M. Baghin, and V. Rao. SSD, page 1481-1486. IEEE, (2018)Circuit Optimization at 22nm Technology Node.A. Sachid, P. Paliwal, S. Joshi, M. Baghini, D. Sharma, and V. Rao. VLSI Design, page 322-327. IEEE Computer Society, (2012)Physics and Technology: Towards Low-Power DSM Design.D. Mukhopadhyay, P. Basu, and V. Rao. VLSI Design, page 16-17. IEEE Computer Society, (2005)Heterogeneous CMOS-MEMS based Boost Converter for 2.4 GHz RF energy Harvester.S. Saha, P. Kanyaka, M. Lust, N. Ghalichechian, V. Rao, and M. Baghini. VLSID, page 425-430. IEEE, (2024)A Low-Power Instrumentation System for Nano-Electro-Mechanical-Sensors for Environmental and Healthcare Applications.S. Surya, S. Nag, N. Duragkar, D. Agarwal, G. Chatterjee, S. Gandhi, S. Patil, D. Sharma, and V. Rao. J. Low Power Electron., 8 (3): 346-352 (2012)A Novel Table-Based Approach for Design of FinFET Circuits.R. Thakker, C. Sathe, A. Sachid, M. Baghini, V. Rao, and M. Patil. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (7): 1061-1070 (2009)Parasitic Effects in Multi-Gate MOSFETs.Y. Kobayashi, C. Manoj, K. Tsutsui, V. Hariharan, K. Kakushima, V. Rao, P. Ahmet, and H. Iwai. IEICE Trans. Electron., 90-C (10): 2051-2056 (2007)Sub-100 nm CMOS circuit performance with high-K gate dielectrics.N. Mohapatra, A. Dutta, G. Sridhar, M. Desai, and V. Rao. Microelectron. Reliab., 41 (7): 1045-1048 (2001)Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies.K. Narasimhulu, and V. Rao. VLSI Design, page 45-50. IEEE Computer Society, (2006)

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Disambiguation of "Rao, V. Ramgopal"