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Другие публикации лиц с тем же именем

Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis., , и . IOLTS, стр. 232-235. IEEE, (2018)Precision tunable RTL macro-modelling cycle-accurate power estimation., и . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)Efficient Functional Locking of Behavioral IPs., и . MWSCAS, стр. 639-642. IEEE, (2020)Autonomous temperature control technique in VLSI circuits through logic replication., и . IET Comput. Digit. Tech., 3 (1): 62-71 (2009)DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures., и . ICCD, стр. 587-594. IEEE Computer Society, (2018)Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration., , и . DAC, стр. 97. ACM, (2019)Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations., и . ICCD, стр. 524-531. IEEE, (2019)Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models., и . ICCAD, стр. 1-8. ACM, (2019)Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs., и . FPT, стр. 193-196. IEEE, (2016)CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis., , и . ISCAS, стр. 1-5. IEEE, (2023)