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Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache., , , и . ISQED, стр. 163-170. IEEE, (2014)Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs., , , , , , и . DATE, стр. 625-630. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Towards high-performance polarity-controllable FETs with 2D materials., , , , , , , , и . DATE, стр. 637-641. IEEE, (2018)Performance analysis of 3-D monolithic integrated circuits., , , , , и . 3DIC, стр. 1-4. IEEE, (2010)Scalable Boolean Methods in a Modern Synthesis Flow., , , , , , , , и . DATE, стр. 1643-1648. IEEE, (2019)Parallel vs. serial inter-plane communication using TSVs., , и . LASCAS, стр. 1-5. IEEE, (2014)A study on buffer distribution for RRAM-based FPGA routing structures., , , и . LASCAS, стр. 1-4. IEEE, (2015)A fast pruning technique for low-power inexact Circuit design., , , , , и . LASCAS, стр. 1-4. IEEE, (2015)Pattern-based FPGA logic block and clustering algorithm., , и . FPL, стр. 1-4. IEEE, (2014)Performance driven reliable link design for networks on chips., , и . ASP-DAC, стр. 749-754. ACM Press, (2005)