Author of the publication

High-speed high-precision CMOS analog rank order filter with O(n) complexity.

, , , and . IEEE J. Solid State Circuits, 40 (6): 1238-1248 (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

High-speed high-precision CMOS analog rank order filter with O(n) complexity., , , and . IEEE J. Solid State Circuits, 40 (6): 1238-1248 (2005)Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard., and . J. Electron. Test., 19 (1): 21-28 (2003)High-speed high-precision analog rank order filter in CMOS technology., , , and . ISCAS (1), page 793-796. IEEE, (2004)A New Power Efficient Fully Differential Low-Voltage Two Stage OP-AMP Architecture., , , and . VLSI, page 87-91. CSREA Press, (2003)New very compact CMOS continuous-time low-voltage analog rank-order filter architecture., , and . ISCAS (1), page 805-808. IEEE, (2003)Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong Inversion., , , and . VLSI, page 345-350. CSREA Press, (2003)New compact CMOS continuous-time low-Voltage analog rank-order filter architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (5): 257-261 (2004)Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard., and . LATW, page 131-134. IEEE, (2001)