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Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids.

, , , and . NEWCAS, page 1-4. IEEE, (2013)

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Challenges in Floorplanning and Macro Placement for Modern SoCs.. ISPD, page 71-72. ACM, (2024)An efficient algorithm for partitioning parameterized polygons into rectangles., and . ACM Great Lakes Symposium on VLSI, page 366-371. ACM, (2006)Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids., , , and . NEWCAS, page 1-4. IEEE, (2013)Flexible chip placement via reinforcement learning: late breaking results., , , , , , , , , and 4 other author(s). DAC, page 1392-1393. ACM, (2022)GBLD: A Formal Model for Layout Description and Generation., and . FDL, page 661-672. ECSI, (2004)Estimation of Analog Layout Parasitics with Parameterized Polygons. University of Queensland, Australia, (2008)Boolean mask operations on parameterized 45-degree polygons., , and . MWSCAS, page 453-456. IEEE, (2013)Constraint-Based Dogleg Channel Routing with Via Minimization., , , and . IC-AI, page 666-672. CSREA Press, (2010)An Automated System for Checking Lithography Friendliness of Standard Cells., , , , , and . APCCAS, page 261-265. IEEE, (2018)A System for Standard Cell Routability Checking and Placement Routability Improvements., , , , , and . APCCAS, page 125-128. IEEE, (2019)