Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors., , , and . IEEE Comput. Archit. Lett., 20 (1): 78-81 (2021)Breaking In-Order Branch Miss Recovery., , , and . IEEE Comput. Archit. Lett., 19 (1): 30-33 (2020)Many-core graph workload analysis., , , , and . SC, page 22:1-22:11. IEEE / ACM, (2018)The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor., , , , , , , , , and 10 other author(s). IEEE Micro, 43 (5): 78-87 (September 2023)Circuit design of a dual-versioning L1 data cache., , , , , and . Integr., 45 (3): 237-245 (2012)Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study., and . CoRR, (2022)Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation., , , and . ISPASS, page 124-133. IEEE, (2023)Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory., , , , , , and . PACT, page 361-371. IEEE Computer Society, (2011)STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems., , , , , , and . PACT, page 221-231. IEEE Computer Society, (2011)Adaptive History-Based Memory Schedulers for Modern Processors., and . IEEE Micro, 26 (1): 22-29 (2006)