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A Speedup Analyzer for Parallel Programs.

, , , and . ICPP, page 653-662. Pennsylvania State University Press, (1987)

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Cache Operations by MRU Change., and . IEEE Trans. Computers, 37 (6): 700-709 (1988)A Stochastic Model of Bin-Packing, , , and . Inf. Control., 44 (2): 105-115 (February 1980)Techniques to Enhance Cache Performance Across Parallel Program Sections., , and . ICPP (1), page 12-19. CRC Press, (1993)Cache Design of a Sub-Micron CMOS System/370., , and . ISCA, page 208-213. (1987)Performance and Design Choices of Level-Two Caches., and . HICSS (1), page 422-430. IEEE Computer Society, (1994)Deterministic Scheduling with Pipelined Processors., , and . IEEE Trans. Computers, 29 (4): 308-316 (1980)Trace Driven Simulation for Studying MIMD Parallel Computers., and . ICPP (1), page 68-72. Pennsylvania State University Press, (1989)Guest Editors' Introduction: Computer Architecture Simulations., and . Int. J. Comput. Simul., 6 (1): 1- (1996)Performance Visualization of Parallel Programs on a Shared Memory Multiprocessor System., , and . ICPP (2), page 1-10. Pennsylvania State University Press, (1989)0-271-00686-2.Memory Access Patterns of Parallel Scientific Programs., , and . SIGMETRICS, page 46-58. ACM, (1987)