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Via design rule consideration in multilayer maze routing algorithms.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (2): 215-223 (2000)

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A Two-pole Circuit Model for VLSI High-speed Interconnection., , , , and . ISCAS, page 2129-2132. IEEE, (1993)A unified optimization framework for simultaneous gate sizing and placement under density constraints., , and . ISCAS, page 1207-1210. IEEE, (2011)General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design., , and . DAC, page 709-715. IEEE Computer Society Press, (1990)High-Performance Clock Routing Based on Recursive Geometric Aatching., , and . DAC, page 322-327. ACM, (1991)Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs., and . DAC, page 704-707. ACM Press, (1998)Accelerator-rich architectures: from single-chip to datacenters.. ISLPED, page 139-140. ACM, (2014)Locality and Utilization in Placement Suboptimality., , , , and . Modern Circuit Placement, Springer, (2007)GRT: A Reconfigurable SDR Platform with High Performance and Usability., , , , , , , and . SIGARCH Comput. Archit. News, 42 (4): 51-56 (2014)Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs., , , , , , , and . DAC, page 29:1-29:6. ACM, (2017)Automated accelerator generation and optimization with composable, parallel and pipeline architecture., , , and . DAC, page 154:1-154:6. ACM, (2018)