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A unified memory network architecture for in-memory computing in commodity servers.

, , , , , , and . MICRO, page 29:1-29:14. IEEE Computer Society, (2016)

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Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems., , and . SLIP, page 1-8. IEEE, (2019)Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory., , , , , and . DAC, page 100. ACM, (2019)Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space., , , , and . ISVLSI, page 637-642. IEEE Computer Society, (2016)Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory., , , , and . DATE, page 800-805. IEEE, (2019)There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes., , , , , and . ISCA, page 678-690. ACM, (2017)Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration., , , , and . ICCAD, page 56. ACM, (2016)Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach., , , , , , , , , and 4 other author(s). MICRO, page 615-628. ACM, (2019)Interconnect Architecture Design for Emerging Integration Technologies. University of California, Santa Barbara, USA, (2020)Network-on-Chip Design Guidelines for Monolithic 3-D Integration., , and . IEEE Micro, 39 (6): 46-53 (2019)Scalable memory fabric for silicon interposer-based multi-core systems., , , and . ICCD, page 33-40. IEEE Computer Society, (2016)