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Disambiguation of "Mohanty, Saraju P."

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A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic.

, , , and . ISVLSI, page 587-590. IEEE Computer Society, (2016)

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Jitendranath Mohanty

Subhasis Mohanty

Sasank Sekhar Mohanty

Jyoti Ranjan Mohanty

Omkar Nath Mohanty

 

Other publications of authors with the same name

Embedding low cost optimal watermark during high level synthesis for reusable IP core protection., , and . ISCAS, page 974-977. IEEE, (2016)Special section on new circuit and architecture-level solutions for multidiscipline systems.. JETC, 8 (3): 14:1-14:2 (2012)Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO., , and . ACM Great Lakes Symposium on VLSI, page 303-308. ACM, (2009)Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective., , , and . ACM Great Lakes Symposium on VLSI, page 145-150. ACM, (2011)Simscape design flow for memristor based programmable oscillators., , , and . ACM Great Lakes Symposium on VLSI, page 223-224. ACM, (2014)A dual watermarking technique for images., , and . ACM Multimedia (2), page 49-51. ACM, (1999)Multi-Phase Obfuscation of Fault Secured DSP Designs With Enhanced Security Feature., , , and . IEEE Trans. Consumer Electronics, 64 (3): 356-364 (2018)IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices., , , and . IEEE Access, (2016)iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization., and . CoRR, (2019)Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (4): 742-755 (2018)