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A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture.

, , , , , and . FPL, page 615-618. IEEE, (2012)

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VLSI architecture of dynamically reconfigurable hardware-based cipher., , , and . ISCAS (4), page 734-737. IEEE, (2001)Measurement of Variations in FPGAs under Various Load Conditions., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2020)NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (7): 1483-1491 (2014)Area-Efficient Reconfigurable Architecture for Media Processing., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3651-3662 (2008)Burst mode: a new acceleration mode for 128-bit block ciphers., , , and . CICC, page 151-154. IEEE, (2002)A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture., , , , , and . FPL, page 615-618. IEEE, (2012)Development of Autonomous Driving System Using Programmable SoCs., , , , , and . FPT, page 453-456. IEEE, (2019)Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1118-1129 (2010)Stress Probability Computation for Estimating NBTI-Induced Delay Degradation., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2545-2553 (2011)Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (7): 1468-1482 (2014)