Author of the publication

An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System.

, , and . VLSI Design, page 863-868. IEEE Computer Society, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A self-sensing tristate pad driver for control signals of multiple bus controllers., , and . ISCAS (1), page 447-450. IEEE, (1999)Characterization of a Fault-tolerant NoC Router., and . ISCAS, page 381-384. IEEE, (2007)A 0.18 µm implementation of a floating-point unit for a processing-in-memory system., , , and . ISCAS (2), page 453-456. IEEE, (2004)Voltage-pulse driven harmonic resonant rail drivers for low-power applications., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 762-777 (2003)A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution., , , and . ACM Trans. Archit. Code Optim., 12 (4): 51:1-51:26 (2016)A Bus-Efficient Low-Latency Network Interface for the PDSS Multicomputer., , , and . HPDC, page 213-222. IEEE Computer Society, (1997)Modeling Data Movement in the Memory Hierarchy in HPC Systems., and . MEMSYS, page 158-161. ACM, (2015)Routing in Bidirectional k-ary n-cubes with the Red Rover Algorithm., and . PDPTA, page 1184-1193. CSREA Press, (1997)Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems., , and . ISCAS (4), page 3331-3334. IEEE, (2005)An area-efficient and protected network interface for processing-in-memory systems., , , and . ISCAS (3), page 2951-2954. IEEE, (2005)