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SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results., , , , and . CoRR, (2024)Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells., , , and . Microelectron. Reliab., 54 (11): 2613-2620 (2014)Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation., , , and . DATE, page 986-991. IEEE, (2011)Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories., , , , and . IOLTS, page 141-146. IEEE Computer Society, (2010)Bit-Cell Selection Analysis for Embedded SRAM-Based PUF., , , and . ISCAS, page 1-4. IEEE, (2020)SRAM-cells Reproducibility Metrics for Physical Unclonable Function Applications., , , and . DCIS, page 1-6. IEEE, (2022)A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors., , , , , and . IEEE Trans. Emerg. Top. Comput., 7 (3): 447-455 (2019)6T CMOS SRAMs reliability monitoring through stability measurements., , and . IOLTS, page 93-95. IEEE, (2017)Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift., and . DTIS, page 1-6. IEEE, (2017)An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies., , , and . Microelectron. Reliab., (2016)