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Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability., , , and . IEEE Micro, 28 (1): 60-68 (2008)Helix: Making the Extraction of Thread-Level Parallelism Mainstream., , , , and . IEEE Micro, 32 (4): 8-18 (2012)Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity., , , , , and . IEEE Micro, 30 (1): 110 (2010)Pipelined parallel architecture for high throughput MAP detectors., , and . ISCAS (2), page 505-508. IEEE, (2004)Evaluation of voltage stacking for near-threshold multicore computing., , and . ISLPED, page 373-378. ACM, (2012)Towards a software approach to mitigate voltage emergencies., , , , and . ISLPED, page 123-128. ACM, (2007)The HELIX project: overview and directions., , , , and . DAC, page 277-282. ACM, (2012)A case for efficient accelerator design space exploration via Bayesian optimization., , , , , , and . ISLPED, page 1-6. IEEE, (2017)Structured Compression by Unstructured Pruning for Sparse Quantized Neural Networks., , , , , and . CoRR, (2019)Network Pruning for Low-Rank Binary Indexing., , , , and . CoRR, (2019)