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Disambiguation of "Anand, Darren"

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Embedded DRAM in 45-nm Technology and Beyond.

, , , and . IEEE Des. Test Comput., 28 (1): 14-21 (2011)

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Davinder Kumar Anand

Darren Gould

Darren Goins

Amar Frank Anand

Madhankumar Anandhakrishnan

 

Other publications of authors with the same name

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 40 (1): 213-222 (2005)Shared fuse macro for multiple embedded memory devices with redundancy., , and . CICC, page 191-194. IEEE, (2001)14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming., , , , , , , and . VLSI Circuits, page 87-88. IEEE, (2018)An On-Chip Self-Repair Calculation and Fusing Methodology., , , , , , and . IEEE Des. Test Comput., 20 (5): 67-75 (2003)Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory., , , , , , and . NATW, page 1-6. IEEE, (2019)Embedded DRAM in 45-nm Technology and Beyond., , , and . IEEE Des. Test Comput., 28 (1): 14-21 (2011)A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2010)Low Cost Test of High Bandwidth Embedded Memories., , , and . CICC, page 445-448. IEEE, (2006)Generating At-Speed Array Fail Maps with Low-Speed ATE., , and . VTS, page 87-96. IEEE Computer Society, (2004)A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST., , , , , , , , , and 1 other author(s). CICC, page 795-798. IEEE, (2007)