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Disambiguation of "Yamawaki, Akira"

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Lower bounds on the number of write operations by index-less indexed flash code with inversion cells.

, , and . ISIT, page 2483-2487. IEEE, (2017)

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Akira Hayashima

Naoshi Yamawaki

Akira Hori

Akira Satake

Akira Hayashima

 

Other publications of authors with the same name

Construction of Parallel Random I/O Codes Using Coset Coding with Hamming Codes., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (12): 2125-2134 (2018)Unrestricted-Rate Parallel Random Input-Output Codes for Multilevel Flash Memory., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (12): 2135-2140 (2018)Tagged communication and synchronization memory for multiprocessor-on-a-chip., , and . Syst. Comput. Jpn., 32 (4): 1-13 (2001)Battery Life Estimation of Sensor Node with Zero Standby Power Consumption., and . CSE/EUC/DCABES, page 166-172. IEEE Computer Society, (2016)Evaluation of mechanisms introduced to improve performance of TSVM cache., and . Parallel and Distributed Computing and Networks, page 502-507. IASTED/ACTA Press, (2004)Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor., and . ISPAN, page 324-333. IEEE Computer Society, (2005)Memory Access Optimization for Former Process of Pencil Drawing Style Image Conversion in High-Level Synthesis., and . PDCAT, volume 13798 of Lecture Notes in Computer Science, page 57-68. Springer, (2022)A Generic Describing Method of Memory Latency Hiding in a High-level Synthesis Technology, and . ACEEE International Journal on Information Technology, 2 (2): 5 (April 2012)Worst-Case Performance of ILIFC with Inversion Cells., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2662-2670 (2017)Omnidirectional Background Scrolling in High-Level Synthesis Oriented Game Programing Library., and . TENCON, page 140-144. IEEE, (2021)