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Disambiguation of "Ren, Fengbo"

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BNN Pruning: Pruning Binary Neural Network Guided by Weight Flipping Frequency.

, and . ISQED, page 306-311. IEEE, (2020)

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Xiaofeng Ren

Xinguo Ren

Ke Ren

Yue Ren

Hongming Ren

 

Other publications of authors with the same name

FSpGEMM: A Framework for Accelerating Sparse General Matrix-Matrix Multiplication Using Gustavson's Algorithm on FPGAs., , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (4): 633-644 (April 2024)A Data-Driven Approach for Automated Integrated Circuit Segmentation of Scan Electron Microscopy Images., , , , , , , and . ICIP, page 2851-2855. IEEE, (2022)Enhanced Low-Resolution LiDAR-Camera Calibration via Depth Interpolation and Supervised Contrastive Learning., , , , , and . ICASSP, page 1-5. IEEE, (2023)Are FPGAs Suitable for Edge Computing?, , and . HotEdge, USENIX Association, (2018)A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only)., , , , and . FPGA, page 290-291. ACM, (2017)A Survey of System Architectures and Techniques for FPGA Virtualization., , and . IEEE Trans. Parallel Distributed Syst., 32 (9): 2216-2230 (2021)Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing., , and . CoRR, (2020)Automatic Error Detection in Integrated Circuits Image Segmentation: A Data-driven Approach., , , , , and . CoRR, (2022)A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks., , , , and . CoRR, (2017)An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 934-938 (2016)