Author of the publication

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management.

, , , , and . CODES+ISSS, page 48-53. ACM, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Who Owns the Platform?, , , , , and . DATE, page 238. IEEE Computer Society, (2002)A future of customizable processors: are we there yet?, and . DATE, page 1224-1225. EDA Consortium, San Jose, CA, USA, (2007)Force-directed scheduling for the behavioral synthesis of ASICs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (6): 661-679 (1989)ReCode: the design and re-design of the instruction codes for embedded instruction-set processors., , and . ED&TC, page 612. IEEE Computer Society, (1997)CodeSyn: a retargetable code synthesis system (abstract)., , , and . HLSS, page 94. ACM, (1994)Logic decomposition algorithms for the timing optimization of multi-level logic., and . ICCD, page 329-333. IEEE, (1989)DATE Panel: Chips of the Future: Soft, Crunchy or Hard?. DATE, page 844-851. IEEE Computer Society, (2004)High-level synthesis and codesign methods: an application to a videophone codec., , , , , , and . EURO-DAC, page 444-451. IEEE Computer Society, (1995)Programming models for network processors (Panel)., , , and . ISSS, page 202. ACM / IEEE Computer Society, (2001)The Future of Flexible HW Platform Architectures Panel Discussion., , , , , and . DATE, page 634. IEEE Computer Society / ACM, (2000)