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An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops.. FPGA, стр. 323. ACM, (2020)A predictive distributed congestion metric with application to technology mapping., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (5): 696-710 (2005)An efficent clustering algorithm for low power clock tree synthesis.. ISPD, стр. 181-188. ACM, (2007)Delay-optimal simultaneous technology mapping and placement with applications to timing optimization., , и . ICCAD, стр. 101-106. IEEE Computer Society, (2008)Parameterized Reusable Component Library Methodology., , и . EUROMICRO, стр. 1410-1415. IEEE Computer Society, (2000)An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.. ISPD, стр. 141-148. ACM, (2009)A predictive distributed congestion metric and its application to technology mapping., , , и . ISPD, стр. 210-217. ACM, (2004)An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis., и . ASP-DAC/VLSI Design, стр. 87-92. IEEE Computer Society, (2002)Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits., и . ICCAD, стр. 449-452. IEEE Computer Society, (2001)BDD decomposition for delay oriented pass transistor logic synthesis., и . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 957-970 (2005)