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Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 217-240. Springer, (2006)3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation., , and . NORCAS, page 1-4. IEEE, (2015)Using 3D integration technology to realize multi-context FPGAs., , , , , , and . FPL, page 507-510. IEEE, (2009)Reconfigurable forward homography estimation system for real-time applications., and . VLSI-SoC, page 1-6. IEEE, (2014)Integration of intra chip stack fluidic cooling using thin-layer solder bonding., , , , , , and . 3DIC, page 1-8. IEEE, (2013)Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits., and . DATE, page 711-716. IEEE Computer Society, (2010)Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies., and . Integr., (2017)Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff., , and . Microelectron. J., 41 (10): 669-679 (2010)Capacitance DNA bio-chips improved by new probe immobilization strategies., , , , , , , , , and 1 other author(s). Microelectron. J., 41 (11): 711-717 (2010)Hardware security in VLSI., and . ACM Great Lakes Symposium on VLSI, page 447-448. ACM, (2011)