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Disambiguation of "Chiang, Pei-Yuan"

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14.7 A 300GHz frequency synthesizer with 7.9% locking range in 90nm SiGe BiCMOS.

, , , and . ISSCC, page 260-261. IEEE, (2014)

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Pei-Jung Chiang

Pei-Wen Chiang

Xing Pei

Pei Xu

Gang Pei

 

Other publications of authors with the same name

A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 54 (5): 1254-1265 (2019)A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS., , , , , and . ISSCC, page 136-137. IEEE, (2013)A Silicon-Based 0.3 THz Frequency Synthesizer With Wide Locking Range., , , and . IEEE J. Solid State Circuits, 49 (12): 2951-2963 (2014)A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW., , , , , , , , , and 16 other author(s). ISSCC, page 1-3. IEEE, (2022)32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels., , , , , , , and . ISSCC, page 444-446. IEEE, (2021)A CMOS 210-GHz Fundamental Transceiver With OOK Modulation., , , , , and . IEEE J. Solid State Circuits, 49 (3): 564-580 (2014)A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO., , , , , , , , and . IEEE J. Solid State Circuits, 56 (12): 3756-3767 (2021)14.7 A 300GHz frequency synthesizer with 7.9% locking range in 90nm SiGe BiCMOS., , , and . ISSCC, page 260-261. IEEE, (2014)