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Dynamically configurable security for SRAM FPGA bitstreams., , and . Int. J. Embed. Syst., 2 (1/2): 73-85 (2006)Communication-Oriented Design Space Exploration for Reconfigurable Architectures., , and . EURASIP J. Embed. Syst., (2007)ELmD: A Pipelineable Authenticated Encryption and Its Hardware Implementation., , , and . IEEE Trans. Computers, 65 (11): 3318-3331 (2016)Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism., , , , , , , , and . VLSI-SoC, page 1-6. IEEE, (2021)Electromagnetic Transmission of Intellectual Property Data to Protect FPGA Designs., , and . VLSI-SoC (Selected Papers), volume 483 of IFIP Advances in Information and Communication Technology, page 150-169. Springer, (2015)A comprehensive hardware/software infrastructure for IP cores design protection., , , and . FPT, page 263-266. IEEE, (2017)Methodology for Efficient CNN Architectures in Profiling Attacks., , , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020 (1): 1-36 (2020)Reducing and smoothing power consumption of ROM-based controller implementations., , , and . SBCCI, page 8-13. ACM, (2010)Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only)., , and . FPGA, page 282. ACM, (2016)Key Reconciliation Protocols for Error Correction of Silicon PUF Responses., , , and . IACR Cryptology ePrint Archive, (2016)