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Disambiguation of "Kawashima, Shoichiro"

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A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip.

, , , , , , , and . IEICE Trans. Electron., 90-C (10): 1941-1948 (2007)

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Sadao Kawashima

 

Other publications of authors with the same name

Bitline GND sensing technique for low-voltage operation FeRAM., , , , , , and . IEEE J. Solid State Circuits, 37 (5): 592-598 (2002)A ferroelectric memory-based secure dynamically programmable gate array., , , , , and . IEEE J. Solid State Circuits, 38 (5): 715-725 (2003)A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip., , , , , , , and . IEICE Trans. Electron., 90-C (10): 1941-1948 (2007)Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)., , , , and . IEEE J. Solid State Circuits, 39 (11): 2024-2031 (2004)A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's., , , , , , and . IEEE J. Solid State Circuits, 33 (5): 793-799 (1998)A 16 kb 1T1C FeRAM test chip using current-based reference scheme., , , , , and . CICC, page 107-110. IEEE, (2002)A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories., , , , , and . IEEE J. Solid State Circuits, 38 (3): 541-549 (2003)An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 98-C (11): 1047-1057 (2015)