Author of the publication

Fast belief propagation process element for high-quality stereo estimation.

, , , , and . ICASSP, page 745-748. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine., , , , , and . IEEE Trans. Circuits Syst. Video Techn., 18 (1): 98-109 (2008)Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform., , and . IEEE Trans. Signal Process., 53 (4): 1575-1586 (2005)Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension., , , , and . J. Signal Process. Syst., 60 (3): 363-375 (2010)Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform., , and . IEEE Trans. Signal Process., 52 (4): 1080-1089 (2004)An efficient and simple VLSI tree architecture for motion estimation algorithms., , and . IEEE Trans. Signal Process., 41 (2): 889-900 (1993)Learning a Code-Space Predictor by Exploiting Intra-Image-Dependencies., , , and . BMVC, page 124. BMVA Press, (2018)Vector quantization using tree-structured self-organizing feature maps., , and . IEEE J. Sel. Areas Commun., 12 (9): 1594-1599 (1994)Hardware architecture design for H.264/AVC intra frame coder., , , and . ISCAS (2), page 269-272. IEEE, (2004)Frame-level data reuse for motion-compensated temporal filtering., , , and . ISCAS, IEEE, (2006)High Throughput CORDIC-Based Systolic Array Design for the Discrete Cosine Transform., , , and . ISCAS, page 85-88. IEEE, (1994)