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An optimal operating point by using error monitoring circuits with an error-resilient technique., , , and . VLSI-SoC, page 69-73. IEEE, (2015)Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study., , , and . DATE, page 885-888. IEEE, (2018)GRASP based metaheuristics for layout pattern classification., , and . ICCAD, page 512-518. IEEE, (2017)Recovery-driven design: a power minimization methodology for error-tolerant processor modules., , , and . DAC, page 825-830. ACM, (2010)Smart non-default routing for clock power reduction., , and . DAC, page 91:1-91:7. ACM, (2013)A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit., , , , , , , and . IEEE J. Solid State Circuits, 57 (11): 3274-3287 (2022)Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor., , , , , and . DATE, page 1077-1082. IEEE, (2022)Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines, and Blocks in Transformers in Computer Vision., , , and . DATE, page 1-6. IEEE, (2023)GRLC: grid-based run-length compression for energy-efficient CNN accelerator., , , , and . ISLPED, page 91-96. ACM, (2020)Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion., , , and . ISOCC, page 254-255. IEEE, (2020)