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Reducing Cache Misses by Loop Reordering.

, , , and . PARCO, volume 33 of John von Neumann Institute for Computing Series, page 541-548. Central Institute for Applied Mathematics, Jülich, Germany, (2005)

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LS-Sig: Locality-Sensitive Signatures for Transactional Memory., , , and . IEEE Trans. Computers, 62 (2): 322-335 (2013)Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm., , , and . IEEE Trans. Computers, 46 (11): 1264-1271 (1997)An image-processing approach to dotplots: an X-Window-based program for interactive analysis of dotplots derived from sequence and structural data., , , , and . Comput. Appl. Biosci., 11 (3): 301-308 (1995)Teaching the Cache Memory System Using a Reconfigurable Approach., , , , and . IEEE Trans. Educ., 51 (3): 336-341 (2008)Unified Locality-Sensitive Signatures for Transactional Memory., , , and . Euro-Par (1), volume 6852 of Lecture Notes in Computer Science, page 326-337. Springer, (2011)Parallelization Strategies for the VMEC Program., , , and . PARA, volume 1541 of Lecture Notes in Computer Science, page 483-490. Springer, (1998)On Automatic Parallelization of Irregular Reductions on Scalable Shared Memory Systems., , and . Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 422-429. Springer, (1999)Enhancing the Parallelization of Sparse Matrices through Dynamic Issues., , and . PDPTA, page 1451-1457. CSREA Press, (1999)CORDIC Processor for Variable-Precision Interval Arithmetic., , and . VLSI Signal Processing, 37 (1): 21-39 (2004)Vienna-Fortran/HPF Extensions for Sparse and Irregular Problems and Their Compilation., , , and . IEEE Trans. Parallel Distributed Syst., 8 (10): 1068-1083 (1997)