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Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems.

, , and . DSD, page 181-187. IEEE Computer Society, (2011)

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A Communication Architecture for a Massively Parallel Message-Passing Multicomputer., , , and . J. Parallel Distributed Comput., 19 (4): 338-348 (1993)Why M-Valued Circuits are Restricted to a Small Niche.. J. Multiple Valued Log. Soft Comput., 9 (1): 109-123 (2003)Hardware features of the static communication network of a parallel architecture., , , and . Microprocess. Microprogramming, 38 (1-5): 19-24 (1993)Standard Microprocessors Versus Custom Processing Elements for Massively Parallel Architectures., and . PaCT, volume 964 of Lecture Notes in Computer Science, page 320-325. Springer, (1995)Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system., and . IEEE Symposium on Computer Arithmetic, page 194-201. IEEE Computer Society/, (1993)Comparing ternary and binary adders and multipliers.. CoRR, (2019)Ternary circuits: why R=3 is not the Optimal Radix for Computation.. CoRR, (2019)Performance of the NAS Benchmarks on a Cluster of SMP PCs Using a Parallelization of the MPI Programs with OpenMP., , and . PaCT, volume 1662 of Lecture Notes in Computer Science, page 339-350. Springer, (1999)High Performance SoC Design Using Magnetic Logic and Memory., , , , , , , , , and 2 other author(s). VLSI-SoC (Selected Papers), volume 379 of IFIP Advances in Information and Communication Technology, page 10-33. Springer, (2011)Performance of CMOS Current Mode Full Adders., , and . ISMVL, page 27-34. IEEE Computer Society, (1994)