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Disambiguation of "Dalt, Nicola Da"

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F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data.

, , , , , and . ISSCC, page 1-2. IEEE, (2015)

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Nicola Da Dalt

Matthew Lynn Dalton

Georg Daltrop

Klaus Daltrop

Ewald Daltrozzo

 

Other publications of authors with the same name

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture., , , , and . IEEE J. Solid State Circuits, 48 (12): 3134-3145 (2013)Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters., , , and . ESSCIRC, page 392-395. IEEE, (2015)A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider., , , , and . ISSCC, page 356-357. IEEE, (2013)F6: Energy-efficient I/O design for next-generation systems., , , , , and . ISSCC, page 520-521. IEEE, (2014)A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology., , , , , and . IEEE J. Solid State Circuits, 37 (7): 959-962 (2002)Signal and Timing Analysis of a Phase-Domain All-Digital Phase-Locked Loop with Reference Retiming Mechanism, , and . 16th International Conference on Mixed Design of Integrated Circuits and Systems, page 681-687. (June 2009)A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS., and . IEEE J. Solid State Circuits, 38 (7): 1275-1278 (2003)ES3: High-speed communications on 4 wheels: What's in your next car?, and . ISSCC, page 515. IEEE, (2013)A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS., , , , and . ISSCC, page 669-678. IEEE, (2006)A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS., , and . ISSCC, page 478-479. IEEE, (2010)