From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Characterization of Locked Sequential Circuits via ATPG., , , и . ITC-Asia, стр. 97-102. IEEE, (2019)Achieving 100% cell-aware coverage by design., , , и . DATE, стр. 109-114. IEEE, (2016)Test chip design for optimal cell-aware diagnosability., , , и . ITC, стр. 1-8. IEEE, (2016)Logic characterization vehicle design reflection via layout rewiring., , , , , и . ITC, стр. 1-10. IEEE, (2016)IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design., , , , и . ICCD, стр. 11-19. IEEE, (2019)Back-End Layout Reflection for Test Chip Design., и . ICCD, стр. 456-463. IEEE Computer Society, (2018)Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle., , , и . VTS, стр. 1-6. IEEE, (2019)A Low Power Test Pattern Generator for BIST., , , , и . IEICE Trans. Electron., 93-C (5): 696-702 (2010)Regularizing Activation Distribution for Training Binarized Deep Networks., , , и . CVPR, стр. 11408-11417. Computer Vision Foundation / IEEE, (2019)CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation., , и . IEEE BigData, стр. 4723-4729. IEEE, (2018)