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Vt balancing and device sizing towards high yield of sub-threshold static logic gates., , , and . ISLPED, page 355-358. ACM, (2007)A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters., and . ARC, volume 7199 of Lecture Notes in Computer Science, page 174-186. Springer, (2012)Design of Seamless Protocol Switching Layer for Voice Over Internet Protocol (Voip) That Switches Between Bluetooth and Ieee 802.11., , , and . International Journal of Software Engineering and Knowledge Engineering, 15 (2): 271-278 (2005)A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor., , , and . A-SSCC, page 301-304. IEEE, (2014)Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs., , , and . FPT, page 53-56. IEEE, (2012)An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials., , and . ASP-DAC, page 210-215. IEEE, (2009)Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA., , , , and . FPL, page 92-97. IEEE, (2007)An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects., , and . FPL, page 615-618. IEEE, (2008)Criticality-based routing for FPGAS with reverse body bias switch box architectures., , and . FPL, page 1-6. IEEE, (2013)ParaLaR: A parallel FPGA router based on Lagrangian relaxation., , and . FPL, page 1-6. IEEE, (2015)