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A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , and . CICC, page 131-134. IEEE, (2005)A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 168-169. IEEE, (2010)A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS., , , , , and . IEEE J. Solid State Circuits, 42 (3): 627-636 (2007)A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid., , , , , and . ISSCC, page 2102-2111. IEEE, (2006)A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 40 (4): 978-985 (2005)500-Mb/s nonprecharged data bus for high-speed DRAM's., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 33 (11): 1720-1730 (1998)Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies., , , , , , and . IEICE Trans. Electron., 89-C (3): 300-313 (2006)A CMOS multichannel 10-Gb/s transceiver., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 38 (12): 2094-2100 (2003)