( en | de | ru )

 

Disambiguation of "Duan, Lide"

Author of the publication

copydeleteadd this publication to your clipboard
Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (12): 2229-2242 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ulla Lidén

Peter Lidén

Lide Liu

Bao Lide

Linshu Duan

 

Other publications of authors with the same name

Two-level soft error vulnerability prediction on SMT/CMP architectures., , and . IISWC, page 78. IEEE Computer Society, (2011)Optimizing Cloud Data Center Energy Efficiency via Dynamic Prediction of CPU Idle Intervals., , and . CLOUD, page 985-988. IEEE Computer Society, (2015)Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read., , , and . ASP-DAC, page 31-36. IEEE, (2016)FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance., , , , and . ACM Trans. Embed. Comput. Syst., 16 (5s): 132:1-132:20 (2017)Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress., , and . CASES, page 20:1-20:2. ACM, (2017)Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions., , and . IEEE Trans. Computers, 59 (5): 593-607 (2010)iCELIA: A Full-Stack Framework for STT-MRAM-Based Deep Learning Acceleration., , , , and . IEEE Trans. Parallel Distributed Syst., 31 (2): 408-422 (2020)Optimal microarchitectural design configuration selection for processor hard-error reliability., , , and . ISQED, page 91-96. IEEE, (2012)CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration., , , and . ICS, page 149-159. ACM, (2018)Designing and evaluating hybrid storage for high performance cloud computing., , and . SysCon, page 1-8. IEEE, (2018)