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Disambiguation of "Gopalakrishnan, Kailash"

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Deep Learning with Limited Numerical Precision.

, , , and . ICML, volume 37 of JMLR Workshop and Conference Proceedings, page 1737-1746. JMLR.org, (2015)

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Saiprasath Gopalakrishnan

Selvi Gopalakrishnan

Gopalakrishnan Venkiteswaran

Vijay Gopalakrishnan

Kailash Mogare

 

Other publications of authors with the same name

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator., , , , , , , , , and 3 other author(s). IEEE Micro, 39 (5): 102-111 (2019)4-Bit Quantization of LSTM-Based Speech Recognition Models., , , , , , , , , and 2 other author(s). Interspeech, page 2586-2590. ISCA, (2021)Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators., , , and . ISPASS, page 240-242. IEEE, (2021)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference., , , , , , , , , and 44 other author(s). ISCA, page 153-166. IEEE, (2021)A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS., , , , , , , , , and 6 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)ScaleCom: Scalable Sparsified Gradient Compression for Communication-Efficient Distributed Training., , , , , , , , , and 1 other author(s). NeurIPS, (2020)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference., , , , , , , , , and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel., , , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2019)PACT: Parameterized Clipping Activation for Quantized Neural Networks., , , , , and . CoRR, (2018)