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Disambiguation of "Xydis, Sotirios"

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Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging.

, , , , and . MobiHealth, page 222-225. ICST/IEEE, (2014)

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Sotirios Siampos

Sotirios Chalkas

Sotirios Giorginis

Sotirios Wlachos

Sotirios Georganas

 

Other publications of authors with the same name

Dataflow Acceleration of Smith-Waterman with Traceback for High Throughput Next Generation Sequencing., , , , , and . FPL, page 74-80. IEEE, (2019)Rusty: Runtime System Predictability Leveraging LSTM Neural Networks., , and . IEEE Comput. Archit. Lett., 18 (2): 103-106 (2019)VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (6): 1204-1208 (2018)Voltage island management in near threshold manycore architectures to mitigate dark silicon., , , and . DATE, page 1-6. European Design and Automation Association, (2014)OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures., , , , , and . ACM Trans. Embed. Comput. Syst., 17 (5): 86:1-86:27 (2018)Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (4): 607-611 (2019)Beyond RSS: Towards Intelligent Dynamic Memory Management (Work in Progress)., , , , , and . MPLR, page 158-164. ACM, (2023)Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend., , and . SAMOS, page 312-319. IEEE, (2016)High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures., , , and . ISVLSI, page 486-487. IEEE Computer Society, (2010)High-level synthesis with coarse grain reconfigurable components., and . IPDPS, page 1-4. IEEE, (2009)