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Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology.

, , , , and . NoCArc@MICRO, page 37-42. ACM, (2010)

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Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches., , and . NoCArc@MICRO, page 31-36. ACM, (2009)System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic., , , and . VLSI-SoC, page 308-313. IEEE, (2011)Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints., , , , , , , and . DATE, page 562-565. IEEE, (2009)Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip., , , and . ACM Great Lakes Symposium on VLSI, page 125-128. ACM, (2009)Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels., , , and . MCSoC, page 159-166. IEEE Computer Society, (2012)Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs., , , , and . DATE, page 679-684. IEEE Computer Society, (2010)A library of dual-clock FIFOs for cost-effective and flexible MPSoC design., , and . ICSAMOS, page 20-27. IEEE, (2010)Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology., , , , and . NoCArc@MICRO, page 37-42. ACM, (2010)Bringing Network-on-Chip links to 45nm., , , and . SoC, page 122-127. IEEE, (2011)A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs., , , , , , , , and . ACM Trans. Embed. Comput. Syst., 12 (4): 106:1-106:29 (2013)