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Analog bandwidth mismatch compensation for time-interleaved ADCs using FD-SOI technology., , , , and . ISCAS, page 1-4. IEEE, (2017)A new algorithm for an incremental sigma-delta converter reconstruction filter., , , and . SBCCI, page 32. ACM, (2019)Synthesis of Subband Hybrid Filter Banks ADCs with finite word-length coefficients using adaptive equalization., , , and . ISCAS, page 577-580. IEEE, (2010)Synthesis of hybrid filter banks for A/D conversion with implementation constraints - mixed distortion/aliasing optimization $., , and . ICASSP (2), page 997-1000. IEEE, (2004)Synthesis of complex subband Hybrid Filter Banks A/D converters using adaptive filters., , and . ICECS, page 399-402. IEEE, (2009)22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS., , , , , , , , , and . ISSCC, page 386-388. IEEE, (2014)A CMOS readout circuit for a low shunt resistance IR photo-detector., , , , and . ICECS, page 1-4. IEEE, (2020)Impacts of Crest Factor Reduction and Digital Predistortion on Linearity and Power Efficiency of Power Amplifiers., , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 407-411 (2019)A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor., , , , and . NEWCAS, page 217-220. IEEE, (2017)Optimization of a pruned 2-D Digital Predistortion Model Structure for Power Amplifiers Linearization., , and . NEWCAS, page 1-4. IEEE, (2019)