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An Incomplete Scan Design Approach to Test Generation for Sequential Machines., , , and . ITC, page 730-734. IEEE Computer Society, (1988)Redundancies and don't cares in sequential logic synthesis., , and . J. Electron. Test., 1 (1): 15-30 (1990)On the verification of sequential machines at differing levels of abstraction., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (6): 713-722 (1988)On the over-specification problem in sequential ATPG algorithms., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (10): 1599-1604 (1993)Redundancies and Don't Cares in Sequential Logic Synthesis., , and . ITC, page 491-500. IEEE Computer Society, (1989)Irredundant sequential machines via optimal logic synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (1): 8-18 (1990)Logic verification algorithms and their parallel implementation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (2): 181-189 (1989)On Efficient and Robust Constraint Generation for Practical Layout Legalization., , , , and . ISQED, page 379-384. IEEE Computer Society, (2008)A Robust Solution to the Timing Convergence Problem in High-Performance Design., , , , , and . ICCD, page 250-257. IEEE Computer Society, (1999)Easily testable PLA-based finite state machines., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (6): 604-611 (1990)