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Disambiguation of "Park, Hong-June"

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A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling.

, , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1645-1656 (2009)

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June Park

Hong-June Kuo

Hong-Yang Park

Hong-Suck Park

Joo-Hong Park

 

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An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation., , , and . IEICE Trans. Electron., 93-C (12): 1662-1669 (2010)A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (5): 629-642 (1991)A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme., , , , , and . IEEE J. Solid State Circuits, 37 (2): 245-250 (2002)A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines., , , , and . IEEE J. Solid State Circuits, 47 (9): 2068-2079 (2012)Analysis and prevention of DRAM latch-up during power-on., , , , , , , , and . IEEE J. Solid State Circuits, 32 (1): 79-85 (1997)A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation., , and . IEEE J. Solid State Circuits, 41 (3): 633-641 (2006)A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC., , , and . Journal of Circuits, Systems, and Computers, 25 (12): 1650155:1-1650155:16 (2016)5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop., , , , and . ISSCC, page 94-95. IEEE, (2017)A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate., , , , , and . ISSCC, page 184-185. IEEE, (2009)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)