Author of the publication

Improving data cache performance with integrated use of split caches, victim cache and stream buffers.

, , , and . MEDEA@PACT, page 41-48. ACM, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Post-compaction register assignment in a retargetable compiler., and . MICRO, page 107-116. ACM/IEEE, (1990)Compiler Optimization for Superscalar Systems: Global Instruction Scheduling without Copies., , and . Digit. Tech. J., (1998)Automatic data partitioning for the agere payload plus network processor., and . CASES, page 238-247. ACM, (2004)Improving Software Pipelining with Unroll-and-Jam., , and . HICSS (1), page 183-192. IEEE Computer Society, (1996)Tiny split data-caches make big performance impact for embedded applications., , , and . J. Embed. Comput., 2 (2): 207-219 (2006)Modulo Scheduling with Cache Reuse Information., , and . Euro-Par, volume 1300 of Lecture Notes in Computer Science, page 1079-1083. Springer, (1997)CRAIG: a practical framework for combining instruction scheduling and register assignment., , , and . PACT, page 11-18. IFIP Working Group on Algol / ACM, (1995)Register Assignment for Software Pipelining with Partitioned Register Banks., , , and . IPDPS, page 211-218. IEEE Computer Society, (2000)Building a Retargetable Local Instruction Scheduler., , , and . Softw. Pract. Exp., 28 (3): 249-283 (1998)Trace scheduling optimization in a retargetable microcode compiler., , and . MICRO, page 106-114. ACM/IEEE, (1987)