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Optimizing pipelined networks of associative and commutative operators.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (11): 1418-1425 (1994)

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Tree-height minimization in pipelined architectures., and . ICCAD, page 112-115. IEEE Computer Society, (1989)Property-specific witness graph generation for guided simulation., , , , , and . DATE, page 799. IEEE Computer Society, (2001)Optimizing pipelined networks of associative and commutative operators., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (11): 1418-1425 (1994)Property-Specific Testbench Generation for Guided Simulation., , , , , and . ASP-DAC/VLSI Design, page 524-. IEEE Computer Society, (2002)MIST - A Design Aid for Programmable Pipelined Processors.. DAC, page 532-536. ACM Press, (1994)A synthesis environment for designing DSP systems., , , , , , , and . IEEE Des. Test, 6 (2): 35-44 (1989)Balancing structural hazards and hardware cost of pipelined processors.. ED&TC, page 562-567. IEEE Computer Society, (1995)Scheduling and hardware sharing in pipelined data paths., , , and . ICCAD, page 24-27. IEEE Computer Society, (1989)Automatic Operator Configuration in the Synthesis of Pipelined Architectures., and . DAC, page 174-179. IEEE Computer Society Press, (1990)Efficient algorithms for interface timing verification., , , and . EURO-DAC, page 34-39. IEEE Computer Society, (1994)