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Circuit-Level Design Approaches for Radiation-Hard Digital Electronics.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (6): 781-792 (2009)

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Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes"., , and . EURASIP J. Embed. Syst., (2009)Circuit-Level Design Approaches for Radiation-Hard Digital Electronics., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (6): 781-792 (2009)TC: Throughput Centric Successive Cancellation Decoder Hardware Implementation for Polar Codes., , and . CoRR, (2015)Overlapped List Successive Cancellation Approach for Hardware Efficient Polar Code Decoder., , and . CoRR, (2015)An Efficient Partial Sums Generator for Constituent Code based Successive Cancellation Decoding of Polar Codes., and . CoRR, (2016)Selective-set-invalidation (SSI) for soft-error-resilient cache architecture., and . SIGARCH Comput. Archit. News, 27 (3): 4-9 (1999)XJ-BP: Express Journey Belief Propagation Decoding for Polar Codes., , and . GLOBECOM, page 1-6. IEEE, (2015)An iterative soft decision based adaptive K-best decoder without SNR estimation., , and . ACSSC, page 1016-1020. IEEE, (2014)Device-Level Transient Fault Modeling., , and . FTCS, page 86-94. IEEE Computer Society, (1994)Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels., , , and . J. Low Power Electron., 5 (3): 303-312 (2009)