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HEBS: Histogram Equalization for Backlight Scaling.

, , and . DATE, page 346-351. IEEE Computer Society, (2005)

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Statistical logic cell delay analysis using a current-based model., , and . DAC, page 253-256. ACM, (2006)A Method of Via Variation Induced Delay Computation., , , , , , , and . DATE, page 1712-1713. IEEE, (2020)A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers., , and . ICCAD, page 504-509. IEEE Computer Society / ACM, (2003)Parameterized block-based non-gaussian statistical gate timing analysis., , and . ASP-DAC, page 947-952. IEEE, (2006)VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input., , and . ACM Great Lakes Symposium on VLSI, page 426-430. ACM, (2005)HEBS: Histogram Equalization for Backlight Scaling., , and . DATE, page 346-351. IEEE Computer Society, (2005)A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect., , , and . DATE, page 568-573. ACM, (2008)VGTA: Variation Aware Gate Timing Analysis., , and . ICCD, page 351-356. IEEE Computer Society, (2005)Non-gaussian statistical interconnect timing analysis., , and . DATE, page 533-538. European Design and Automation Association, Leuven, Belgium, (2006)Crosstalk timing windows overlap in statistical static timing analysis., and . ISQED, page 245-251. IEEE, (2013)