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Disambiguation of "Choi, Michael"

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A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling.

, , , , , , , , and . IEEE J. Solid State Circuits, 53 (4): 1139-1148 (2018)

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Michael Choi

Andreas Choi

Bongkyung Choi

Jinsub Choi

Carmen Choi

 

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A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (9): 2532-2542 (2019)A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS., and . IEEE J. Solid State Circuits, 36 (12): 1847-1858 (2001)Recent Developments of the Space Exploration Synthetic Aperture Radar (SESAR) for Planetary Science Missions., , , , , , , , , and 4 other author(s). IGARSS, page 7839-7842. IEEE, (2021)3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor., , , , , , , and . ISSCC, page 70-72. IEEE, (2024)A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 172-173. IEEE, (2022)A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL., , , , , , and . CICC, page 1-2. IEEE, (2023)A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC., , , , , , and . A-SSCC, page 1-3. IEEE, (2023)Imperfect information transmission and adverse selection in asset markets.. J. Econ. Theory, (2018)A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation., , , , , , , , , and 2 other author(s). VLSIC, page 1-2. IEEE, (2014)A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control., , , , , and . CICC, page 1-4. IEEE, (2012)