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Disambiguation of "Subramanian, Lavanya"

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BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling.

, , , , and . IEEE Trans. Parallel Distributed Syst., 27 (10): 3071-3087 (2016)

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Lavanya Natesan

Lavanya Sharan

Lavanya Sivashanmugam

Lavanya Babujee

Pallavi Subramanian

 

Other publications of authors with the same name

Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism., , , , , , , , and . CoRR, (2016)GrandSLAm: Guaranteeing SLAs for Jobs in Microservices Execution Frameworks., , , , , and . EuroSys, page 34:1-34:16. ACM, (2019)BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling., , , , and . IEEE Trans. Parallel Distributed Syst., 27 (10): 3071-3087 (2016)Social Networking Sites: College Students' Patterns of Use and Concerns for Privacy and Trust by Gender, Ethnicity, and Employment Status., , and . Int. J. Inf. Commun. Technol. Educ., 12 (4): 62-75 (2016)High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems., , , , and . CoRR, (2018)Providing High and Controllable Performance in Multicore Systems Through Shared Resource Management.. CoRR, (2015)Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost., , , , , and . CoRR, (2018)DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators., , , and . ACM Trans. Archit. Code Optim., 12 (4): 65:1-65:28 (2016)MISE: Providing performance predictability and improving fairness in shared main memory systems., , , , and . HPCA, page 639-650. IEEE Computer Society, (2013)FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity., , , , , , , , , and 1 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 31:1-31:35 (March 2023)