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FPGA Implementation of a Channelizer with 2048 Channels Utilizing USRP-SDR Platform for Satellite Communications., , , , , and . ApplePies, volume 512 of Lecture Notes in Electrical Engineering, page 25-31. Springer, (2017)Hardware design of LIF with Latency neuron model with memristive STDP synapses., , , , , , , and . CoRR, (2018)A Reconfigurable Functional Unit for Modular Operations., , , , and . ApplePies, volume 289 of Lecture Notes in Electrical Engineering, page 141-152. Springer, (2013)Improved Large-signal Model for Vacuum Triodes., , and . ISCAS, page 3006-3009. IEEE, (2009)Power-delay tradeoffs in residue number system., , and . ISCAS (5), page 413-416. IEEE, (2003)Low-power adaptive filter based on RNS components., , , , and . ISCAS, page 3211-3214. IEEE, (2007)ADAPTO: full-adder based reconfigurable architecture for bit level operations., , , and . ISCAS, page 3434-3437. IEEE, (2008)Comparison and Implementation of Variable Fractional Delay Filters for Wideband Digital Beamforming., , , , , , and . ApplePies, page 445-451. Springer, (2018)Karatsuba implementation of FIR filters., , , and . ACSCC, page 1111-1114. IEEE, (2012)Partial reconfiguration in the implementation of autonomous radio receivers for space., , , and . ReCoSoC, page 1-6. IEEE, (2011)